This invention relates to Computer Aided Design (CAD) systems; and more particularly, it relates to CAD software programs which lay out physical interconnections for logic circuits on an integrated circuit substrate.
As one example, the above logic circuits can be a variety of logic cells and the above substrate can be a single semiconductor chip. As another example, the logic circuits can be several integrated circuit chips and the substrate can be a multichip ceramic wafer. In a typical CAD system, a library of many different types of logic circuits is provided; and from that library, certain logic circuits are selected for placement on each particular substrate. Usually, a logic cell library contains over one hundred different types of cells such as various types of NAND gates, NOR gates, AND gates, OR gates, multiplexers, latches, flip-flops, etc.; and several thousand of such cells are usually placed on a single semiconductor chip.
Each logic circuit has one or more input terminals and one or more output terminals; and, those terminals need to be selectively interconnected on the substrate. A listing of which terminals are to be connected together is provided by a netlist. Given the netlist and the list of circuits that are selected from the library, the problem arises of precisely where on the substrate each of the selected circuits and each of the circuit interconnections should be physically located. As the number of circuits plus the number of interconnections increases, solving the above "layout" problem becomes more and more tedious.
Originally in the prior art, the above layout problem was solved as follows. To begin, a design engineer or technician assigned specific locations on the substrate to each of the logic circuits. This was done by defining a fixed x, y coordinate system on the substrate, and by giving specific x and y dimensional coordinates to each of the circuits. Thereafter, a CAD software program received as an input the x and y dimensional coordinates of each of the circuits along with the netlist; and as an output the CAD program provided specific x and y dimensional coordinates to each of the circuit interconnections. In performing this task, the CAD program performed a global routing step in which certain open channels were found for each interconnection, and it performed a detailed routing step in which specific x, y dimensional coordinates were assigned to each interconnection in its channel.
Later in the prior art, another CAD layout system called a symbolic layout CAD system was developed. With the symbolic layout CAD system, a design engineer or technician graphically locates the logic circuits by electronically arranging various symbols that represent those circuits on CRT screen. Typically, the symbols are moved on the CRT screen by means of an electromechanical "mouse". Also the design engineer/technician uses the mouse to draw lines on the CRT screen from one symbol to another, as a representation of physical conductors between the logic circuits. Then, after the desired arrangement of the symbols and lines is made, another CAD program called a "Compactor" assigns dimensional x and y coordinates to each of the circuits and conductors that correspond to symbols and lines.
A problem however, with both of the above described processes is that they are too inflexible to accommodate certain changes to the physical layout of the cells and their interconnections which inevitably need to be made multiple times during the design and checkout of any new project. For example, such a change is needed to correct each error in the design, and to accommodate each new functional requirement of the design, and to comply with each change in the layout rules. With the above CAD systems, each time the physical layout of the logic circuits on the substrate changes, all of the layout steps for the logic circuit interconnections need to be repeated; and, that costs both time and money.
Accordingly, a primary object of the invention is to provide a novel CAD process in which the logic circuits can be moved on the substrate and the layout of the interconnections can be obtained without repeating all of the layout steps from the scratch.